1. Field of the Invention
The present invention relates to a semiconductor device having improved soft error resistance.
2. Description of the Prior Art
First of all, assume the case of electrically connecting a source/drain that is an impurity-diffused layer and a gate electrode wiring existing on a separating area. Herein, the source drain is formed with an impurity-diffused layer having a conduction type opposite to that of the silicon substrate (or the well area). The gate electrode wiring is often formed with polysilicon.
An electrical connection is usually performed by opening a contact hole on a portion of the gate electrode wiring on the separating area and another contact hole on a portion of the diffused layer, individually, followed by covering these contact holes in common with a metal such as aluminum or tungsten. In that case, such an electrical conduction is achieved by opening one common contact hole across the above-mentioned gate electrode wiring and the diffused layer, followed by covering the contact hole with the metal, rendering a smaller occupied area.
FIG. 30 and FIG. 31 are respectively a plan view and a sectional view taken along line Ixe2x80x94I of FIG. 30, which show the structure of a common contact hole described in JP-A 61/168265(1986) of the prior art. FIGS. 30 and 31 show a well area 10, a diffused layer 20, a gate electrode 30, an interlayer film or dielectric 50, and a common contact hole 60. This common contact hole 60 has a structure in which the gate electrode 30 and the diffused layer 20 corresponding to source/drain are situated at some distance to prevent their overlapping. This is to avoid a problem that the gate electrode 30 and the substrate 10 may be shorted by passing the gate electrode 30 through the thin gate oxide film under the gate electrode when the gate electrode 30 extends onto the silicon substrate. Actually, a sidewall of SiO2 is provided in an isolation portion between the gate electrode 30 and diffused layer 20 in order to avoid the short between the gate electrode 30 and the substrate. However, this structure is not illustrated in FIGS. 30 and 31 for simplicity.
Japanese Patent No. 3,064,999 illustrates the structure of a common contact hole when a silicide layer and a gate sidewall are adopted. The structure is devised to place the center of the common contact hole 60 in the central position of the gate sidewall in order to increase positional margin or accuracy against mask dislocations.
JP-A 08/125137(1996) describes the example in which a resistor is inserted in the common contact hole in order to reduce soft-error.
Since a conventional semiconductor device is configured as mentioned above, with the microfabrication of memory cells, there appears manifestly a soft-error problem that the data held in memory nodes could be inverted by external causes such as alpha rays emitted from a package or electrons generated by neutron beams from space. Especially, the malfunction has become serious as the power supply voltage decreases.
As a countermeasure for increasing soft error resistance, there is a method of decreasing the inversion of memory data brought by the external cause by increasing a capacitance of a memory node (referred to as critical charge). However, in the method, there are drawbacks such as increase of area and cost-up because of required additional processes in order to create the capacitance.
The present invention has been accomplished to solve the above-mentioned problems, and is directed to a semiconductor device that has a small cell size and improved soft-error resistance.
First, the present invention provides a semiconductor device, comprising:
a gate electrode formed on a substrate through a gate insulating film lying therebetween; a first and a second diffused layers formed opposed to each other across the portion of the substrate existing under the gate electrode and having a first conduction type, each having a second conduction type different from the first conduction type of the portion; a wiring layer formed above the gate electrode; a contact hole formed between the wiring layer and the substrate; and a semiconductor device, comprising:
a gate electrode formed on a substrate through a gate insulating film lying therebetween; a first and a second diffused layers formed opposed to each other across the portion having a first conduction type of the substrate under the gate electrode, each having a conduction type different from the first conduction type of the portion; a wiring layer formed above the gate electrode; and a contact formed within a contact hole between the wiring layer and the substrate, which connects the wiring layer to the first diffused layer and the gate electrode.
Herein, the contact may be connected also to the second diffused layer.
In addition, the semiconductor device comprises a third diffused layer formed on the substrate, and an isolation area formed between the first and the third diffused layers, which separates the first and the third diffused layers each other; and the contact may be connected further to the third diffused layer.
Second, the present invention provides a semiconductor device, comprising: a gate electrode formed on a substrate through a gate insulating film; a diffused layer formed on the substrate; a wiring layer formed above the gate electrode; and a contact formed within a contact hole between the wiring layer and the substrate, which connects the wiring layer to the diffused layers and the gate electrode; wherein the diffused layer has: a first and a second portions formed opposed to each other across the portion of the substrate existing under the gate electrode and having a first conduction type, each having a second conduction type different from the first conduction type of the portion of the substrate; and a third portion that connects the first portion to the second portion.
Herein, the contact may be connected to the first and the second portions of the diffused layer.
In addition, the semiconductor device comprises another diffused layer formed on the substrate, and an isolation area formed between the diffused layer and the other diffused layer, which separates the diffused layer and the other diffused layer; and the contact may be connected further to the other diffused layer.
The semiconductor device comprises a SRAM cell, and the wiring layer may be connected to the memory node of the SRAM cell.
The semiconductor device comprises a bistable trigger circuit, and the wiring layer may be connected to the memory node of the bistable trigger circuit.
The semiconductor device comprises another gate electrode formed on the substrate through another gate insulating film, and a transistor for composing a semiconductor integrated circuit (IC) therein; and the film thickness of the gate insulating film may be thinner than the one of the other gate insulating film.
The semiconductor device comprises another gate electrode formed on the substrate through another gate insulating film, and a transistor for composing a semiconductor IC therein; and the relative dielectric constant of the gate insulating film may be higher than the one of the other gate insulating film.
The semiconductor device comprises a source area and a drain area formed opposed to each other across the channel portion of the substrate existing under the gate electrode, and a transistor for composing a semiconductor IC therein; and the impurity concentrations of the first and the second diffused layers may be higher than the ones of the source and the drain areas.
The semiconductor device comprises a source area and a drain area formed opposed to each other across the channel portion of the substrate existing under the gate electrode, and a transistor for composing a semiconductor IC therein; and the impurity concentration of the diffused layer may be higher than the ones of the source and the drain areas.